There is a computer architecture which has a memory shared by a plurality of processors (i.e., a shared memory) and employs a directory-based protocol in coherence control. Patent Document 1 discloses an example of an information processing device which guarantees the global visibility of an invalidation request to an Acquire side processor at the time of a memory order guarantee based on a release consistency model in the abovementioned architecture.
The information processing device disclosed by Patent Document 1 has a plurality of processors, a shared memory, and a network connecting the processors with the shared memory. Each of the processors includes a cache, a memory access control part controlling an access by the processor to the shared memory, and an invalidation request control part executing a cache invalidation process on the basis of an invalidation request by the shared memory. The shared memory transmits a cache invalidation request to the invalidation request control part of an acquire side processor retrieving data, on the basis of a Store instruction by a Release side processor writing data, and transmits an Ack (acknowledgment) representing that the Store instruction has been correctly received to the release side processor.
The memory access control part of the Release side processor has a store counter which is incremented when issuing a Store instruction to the shared memory and is decremented when receiving an Ack representing that a Store instruction has been correctly received from the shared memory, and a wait counter which, when the store counter is decremented to 0, is set to a value representing a predetermined time and is decremented every unit time. When the store counter and the wait counter are decremented to 0, the memory access control part of the Release side processor issues a Store Fence instruction to request the guarantee of completion of invalidation of the cache of the Acquire side processor.
After the cache invalidation process is completed on the basis of the invalidation request by the shared memory, the memory access control part of the Acquire side processor issues a Load Fence instruction to guarantee completion of invalidation of the cache in response to the Store Fence instruction.    Patent Document 1: U.S. Pat. No. 9,606,923. B2(JP Patent 5,811,245 B)
In the information processing device disclosed by Patent Document 1, the shared memory transmits a cache invalidation request to the invalidation request control part of the Acquire side processor retrieving data, on the basis of a Store instruction by the Release side processor writing data, and transmits an Ack representing that the Store instruction has been correctly received to the Release side processor. Because one Ack is returned every time one Store instruction is executed, there is a problem that load on the network connecting the plurality of processors with the shared memory is heavy.